1. Field of the Invention
The present invention relates to an ESD (Electro Static Discharge) protective element, especially an ESD protective element which can be embedded in a high voltage semiconductor integrated circuit formed on a silicon-on-insulator (SOI) substrate.
2. Description of the Related Art
In recent years, MOS-type integrated circuits formed on a silicon-on-insulator (SOI) substrates have expanded into various kinds. More specifically, such integrated circuits can be roughly divided into LSIs used in CPUs for example, of which a high-speed operation with low power consumption is required, and high-voltage ICs used in vehicles and flat display panels (FDP) for example. In general, in a semiconductor integrated circuit high voltage and/or high-current such as a noise surge caused by electrostatic discharge (ESD) may be input to or occasionally output from a voltage/current input/output pad electrode for example. However, semiconductor devices having an SOI structure have poor heat dissipation because it is surrounded with insulating films such as a silicon oxide film having low thermal conductivity, its temperature increase during an ESD event is larger than that of semiconductor devices using an ordinary bulk silicon substrate, it can be easily thermally destructed, and therefore it is believed to be inferior in terms of ESD overloading tolerance.
Such a situation is not limited to circuits comprising semiconductor devices, but also applies to an SOI-type ESD protective element embedded together with the circuit(s). Described in U.S. Pat. No. 4,989,057 (Prior Art Document 1) is a MOS-type ESD protective element structure in high-speed MOS-type semiconductor circuit which has an SOI structure and is driven at a lower voltage than a few voltage of the power supply V, wherein even if a surge is input, heat generation is suppressed to prevent destruction of the ESD protective element, and a satisfactory ESD overload tolerance can be secured. Shown in FIG. 7 is a cross-sectional view of the ESD protective transistor described in Prior Art Document 1.
In FIG. 7 an embedded insulating film 2 is formed on a supporting substrate 1, on which is formed an island-shape low-concentration P-type semiconductor layer 3, which is the basis of an ESD protective element. Then, both ends of the semiconductor layer 3 consist of an N-type source region 4 and a drain region 5. In addition, a gate electrode 7 is set on the semiconductor layer 3 via a thin gate insulating film 6. In an integrated circuit, the gate electrode 7 of the ESD protective transistor is connected to the source region 4 and further connected to a chip ground bus for example. The drain region 5 is connected to wirings and bonding pads having the possibility of surge input, and the P-type semiconductor layer 3 sandwiched by the source region 4 and the drain region 5 is set to an electrically floating state. In another connection mode of the ESD protective transistor, the source region 4 is connected to wiring and bonding pads having the possibility of surge input, and the drain region 5 is connected to the power supply line.
Shown in FIG. 8 shows current-voltage characteristics relating to the breakdown characteristics exhibited by the ESD protective transistor in FIG. 7 when a surge is input. When an applied voltage increases with a reverse bias of the transistor applied, the reverse breakdown voltage of about 12 V (Point A) is reached, and when the current slightly increases from that point a snap-back immediately occurs, with a holding voltage of about 7 V (Point B) which is the minimum voltage applied to the element. Then, as the current continues to increase, the voltage also keeps slightly increasing due to the resistance existing between the source region 4 and the drain region 5. Although not shown here, as the current further increases, breakdown occurs again, and the ESD protective transistor itself reaches a point of thermal destruction.
As described above, in the SOI-type ESD protective transistor described in Prior Art Document 1, when a large surge current is input, a snap-back immediately occurs due to the floating-body effect caused by setting its P-type semiconductor layer 3 into an electrically floating state, and the voltage between the both ends of the source/drain of the ESD protective transistor becomes about 7 V (holding voltage) which is close to half the reverse breakdown voltage of about 12 V. By this the power consumption due to the surge decreases, and the amount of heat generated in the ESD protective transistor decreases in comparison with conventional ones. Therefore, the SOI-type ESD protective transistor becomes capable of dealing with larger surge currents.
The above is an example of applying an ESD protective element to a high-speed SOI-type semiconductor integrated circuit. As semiconductor devices manufactured with an SOI structure, there are also the high (breakdown) voltage semiconductor integrated circuits mentioned above. Assumed as high-voltage semiconductor integrated circuits are MOS-type integrated circuits, such as a scan driver which drives/controls a PDP (plasma display panel), which require a power supply voltage of 150˜300 V, typically about 200 V. Shown in FIG. 9 is the outline circuit diagram of a PDP scan driver IC circuit.
In FIG. 9, connected to the output terminal of the circuit are the PDP electrodes (not shown), and connected are a high voltage P-channel MOS transistor 22 (Pch3), a high voltage insulated gate bipolar transistor (IGBT) 25, and a high voltage diode 26. In the preceding stage of the output stage constituted of these output power elements, high voltage P-channel MOS transistors 20 (Pch1), 21 (Pch2), and high voltage N-channel MOS transistors 23 (Nch1) and 24 (Nch2), which perform the level-shifting operation, are connected, and further a 5-V system low-voltage CMOS control circuit 27 is connected to MOS transistors 23 and 24 and the gate electrode of the IGBT 25. The driving circuit in FIG. 9 is a unit-cell circuit, many of which are connected in parallel between the high-voltage power supply line and the ground (GND) line inside an actual PDP scan driver chip. Because high breakdown voltage elements such as the P-channel MOS transistor 22 and the IGBT 25 of which the output stage of the scan driver is constituted are relatively large in size, a certain degree of ESD tolerance is held by these elements themselves.
However, if the scan driver circuit has low output current in its specification, from the viewpoint of reducing the chip size and suppressing the manufacturing cost to the extent possible, the channel width immediately below the gate electrodes of the high voltage IGBT 25 and the high voltage P-channel MOS transistor 22 is reduced. However, because the ESD tolerance in the output stage decreases if the channel width is reduced, a new ESD protective element is installed.
Shown in FIG. 10 is a chip outline planar layout of a case in which the ESD protective element of Prior Art Document 1 as illustrated in FIG. 8 is placed inside a PDP scan driver (high voltage semiconductor integrated circuit device) chip. Inside a chip 29 such as the PDP scan driver, multiple unit circuit cells are arranged horizontally and vertically with the scan driver circuit in FIG. 9 as the unit circuit cell in a region 30 for forming high voltage semiconductor circuits constituted of an IGBT 25, a diode 26, and transistors 20˜24, and in a region 33 for forming low-voltage semiconductor circuits such as the 5V-system CMOS control circuit 27.
The conventional ESD protective element is formed in an ESD protective element formation region 31 set up in every unit circuit cell. More specifically, by referring the scan driver circuit in FIG. 9, one ESD protective element is connected between the high-voltage power supply line and the output terminal on the side closer to the output terminal than to the P-channel MOS-type transistor 22, and another between the output terminal and the ground line on the side closer to the output terminal than to the IGBT 25 or the high voltage diode 26. One reason that this is necessary for every unit cell is because a conventional ESD protective element has a smaller current capacity at the trigger voltage.